Matrix For Matrix Multiplication

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PROJECT REPORT

IMPLEMENTATION OF FADDEEV’S ALGORITHM IN VHDL for Matrix Multiplication.
(CHAUNG and HE’S IMPLEMENTATION)

Name: G. Shashank Reddy
Enrolment No: AAA0146

Description
In this project we are implementing Chaung He’s systolic implementation using faddeev’s algorithm. These two implementations have their own advantages and drawbacks..
The contents of the REPORT will be as follows

1. What is systolic architecture? and how it can be implemented for matrix multiplication.
2. Gaussian elimination of matrix for matrix computation.
3. Faddeev’s algorithm.
4. Chaung and He’s implementation.

What is Systolic Architecture?
A systolic array comprises of matrix like rows of data processing units called cells. Each cell gives the information to its neighbouring cell instantly after processing. The array is usually rectangular where data flows across the array between neighbouring cells, usually with different data moving in different directions.
Systolic algorithm might be designed for matrix multiplication which is fed in one row at a time from the top of the array and is passed down the array. The other matrix is fed in a column at a time from the left hand side of the array and is passed on from left to right.
There are many types of systolic array:
1. 1d array
2. 2d array
3. Hex array etc.
In Chaung and he’s implementation we use 2-d array.

Applications:
• Systolic arrays for matrix multiplication
• Convolution
• Image processing
• Robotics etc.

Gaussian Elimination for Matrix multiplication.
This process comprises of two parts. The first part is called Forward elimination which reduces a given system to either triangular form , resulting in an equation, indicating the system has no unique solution but may have m...

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...on with out pivoting and the upper half of the data i.e. matrices A and B also use Gaussian elimination but with pivoting (meaning the data rotates).This implementation is quite less expensive when it comes to delay time and hardware complexity.

Since there are Two different phases processing which are required for the upper half and lower half of the data, two separate programs are required for boundary cells and internal cells respectively i.e predefined functions will be formulated to carry out matrix multiplication.
Findings from the Project:
Chaung and He’s implementation is quite simple as compared to other implementations since it does not involve any hard mathematical logic to program in VHDl . This algorithm usually has some timing issues, but works just fine and this implementation is not synthesizable. The performance efficiency is also quite good.

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