Test-data compression using statistical coding and linear decompressors

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Owing to the fact that testers such as ATE have limited memory, speed and I/O channels, and the amount of test data that is processed in and out of ATE is directly proportional to the cost of operation. In practice, the test data bandwidth comes as a bottleneck in speeding up testing to cut test time. Test data compression reduces the amount of data stored on the tester and more importantly, given the test data bandwidth, reduces the test time. Our goal is to summarize recent trends in test compression especially statistical coding and LFSR reseeding. 1. Introduction The trade-off involving fault coverage, test application time and test-data compression has been at the heart of research in design for testability. The alluring aspect of test-data compression is that it requires minimal changes to traditional design flow. A test cube is a deterministic test vector in which the bits that the Automatic Test Pattern Generator (ATPG) does not assign are left as don’t cares. Test cubes tend to be highly correlated because faults are structurally related in the circuit. By exploiting both these factors, high amount of compression can be achieved. Test vector compression schemes fall into following broad categories: Code-based schemes Linear-decompression-based schemes (LFSRs and XOR networks) Over the years, several code-based test compression schemes have been proposed for encoding test vectors of a circuit under test (CUT). Alternating run-length codes were suggested in [1], FDR codes in [2], [4], Golomb codes in [3], [7], statistical codes in [5], [6] and code combinations in [8]. One class of coding schemes, called statistical coding, represent frequently occurring code words with fewer bits and those t... ... middle of paper ... ...onf., pages 301–310, 2002. [15]V. Chickermane, B. Foutz, and B. Keller. “Channel Masking Synthesis for Efficient On-Chip Test Compression,” Proc.of IEEE Intl’ Test Conf., pages 452–461, 2004. [16]H. Tang and et. al. “On Efficient X-Handling Using a Selective Compaction Scheme to Achieve High Test Response Compaction Ratios,” Proc. Intl’ Conf. on VLSI Design, pages 59–64, 2005. [17] Y. Tang and et al. “X-Masking During Logic BIST and Its Impact on Defect Coverage,” Proc. IEEE International Test Conf., pages 442–451, 2004. [18] SeongmoonWang ,Kedarnath J. Balakrishnan , Srimat T. Chakradhar, “Efficient unknown blocking using LFSR reseeding,”Proc. of the conf. on Design, automation and test, March 06-10, 2006, Munich, Germany [19] A. Al-Yamani and E. J.McCluskey, “Seed Encoding with LFSRs and Cellular Automata,” Proc. of Design Automation Conf., pages 560–565, 2003.

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