Single Event Effect Essay

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Reliability is one of the most important factors in circuit design. For modern CMOS technology, the circuit reliability is influenced by the shrinking of technology, the reduced supply voltage, higher frequency, and higher circuit density. These factors affects the circuit's probability of soft errors (also called single event upset). In addition, the process variation introduced in the fabrication process is also a big challenge for circuit designers because it makes the same circuit show different characteristics. Moreover, to reduce power consumption of the circuit, the method of reducing supply voltage to near threshold region is used, which is anticipated to have more effects on the reliability of the circuit. So the relationship between single event effect and process variation under near-threshold supply voltage should be analyzed and discussed.

The backgrounds related to the main concepts in this thesis are discussed in the remaining part of this chapter.

section{Single event effects}
A single event effect is a circuit or system response to charge deposition from a single ionizing particle cite{1208578}cite{1545891}. Single event effects can induce destructive and nondestructive damage to the circuit. In this thesis, only the nondestructive single event effect is taken into account.

The basic mechanism for the single event effect in microelectronics includes the charge deposition and the charge collection. In the charge deposition process, there are two ways to release charge in semiconductor devices: (1) direct ionization is caused by the incident particles, and (2) indirect ionization is caused by the nuclear reaction between the incident particle and the device. Usually the deposition mechanism for heavy ions...

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...y the dependence of critical charge variation on gate length variation, threshold variation, and correlation between gate lengths. Also a simple model is presented to estimate critical charge variation without Monte Carlo simulation cite{4063059}.

In previous studies, most of the circuits analyzed operate at the nominal supply voltage. Some research also takes the supply voltage into account. In cite{5580133} by Mostafa et al., one analytical model is developed to explain the impact of supply voltage on critical charge and its variability of 65-nm 6T SRAM cell. The coupling capacitor is found to mitigate the impact of process variations on critical charge variability cite{5580133}.

In the near-threshold region, results in Fig. ef{fig:sevoltage} show that circuits are more vulnerable to soft errors. As supply voltage decreases, the soft error rate increases.
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