Motorola Microprocessor

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MOTOROLA 68060 - PERFECT SOLUTION FOR NETWORKING AND EMBEDDED SYSTEM Introduction: What is the heart of a computer system? Of course, that is the CPU. In general, CPU is composed from a microprocessor that controls all the operations of the system. In the IT market today, there are many kinds of microprocessors available to build the CPU, such as Intel, AMD, Cyric, Alpha… each of them has its own advantages and is used for separated purposes. In this document, I'd like to discuss about a high performance microprocessor, the newest Motorola's 32-bit microprocessor MC68060, which is widely used in networking technology and embedded systems. Section 1 will introduce an overview about the architecture of this microprocessor and its functional blocks. The processing states of the microprocessor are described in section 2. Section 3 refers briefly to programming model - data registers, data format. For instruction set list, please refer to the source of information at the end of this document. 1. Microprocessor architecture: Motorola microprocessor has several main functional blocks: the execution unit, memory units, and bus controller, as we can see in the figure below: a) The Execution Unit: consisted of Instruction Fetch Unit, Integer Unit and Floating Point Unit. Instruction Fetch Unit is the unit that the microprocessor fetches the next instruction to be executed in. This unit establishes and manages the pipeline mechanism, which allows 4-stage pipelining of instructions: Instruction Address Calculation (IAG), Instruction Fetch (IC), Early Decode (IED), and Instruction Buffer. This smooth fetching keep the CPU always busy and bring the greatest performance. MC68060 uses branch cache to let the instruction fetch pipeline notice about the branch instructions such as jmp or procedures, and change the instruction stream timely. Integer Unit carried out logical and arithmetic operations. This unit also uses dual pipeline mechanism with superscalar design that allows the microprocessor do three instructions simultaneously in each clock cycle. The pipeline in Integer Unit has 6 stages that are decode (DS), Effective Address Calculation (AG), Effective Address Fetch (OC), Integer Execution (EX), Data Available (DA), write back (WB). Floating Point Number, with its different format, is processed in Floating Point Unit (FPU). FPU operates in parallel with integer unit. b) Memory Unit: includes Instruction Memory Unit and Data Memory Unit, each works independently from the other. Each of them has 8Kbyte cache, which is accessed by physical address, a cache controller and an ATC (Address Translation Cache). The 64-entry, 4 way, set-associative ATCs store recently used logical to physical address translation information as page descriptors for instruction and data accesses.

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