0.5 mm2 All-Digital SAW-less Polar Transmitter for EDGE in 65 nm CMOS

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EDGE is currently the most widely used standard for data communications in mobile phones. Its proliferation, supported by its backward compatibility with GSM, has led to a need for low-cost EDGE mobile solutions. The implementation of RF circuits on the nanoscale digital CMOS process with no or minimal process enhancements is one of the key obstacles limiting the complete single-chip integration of cellular radio functionality with digital baseband for mass production. The key challenges for the RF integration in nanoscale CMOS include non-linearity of devices and circuits, device mismatches, process parameter spread, and the increasing potential for self-interference that could be induced by one function in the SoC onto another. The presented transmitter is part of a fully-compliant EDGE SoC and successfully overcomes these challenges at low cost. It is the first to successfully demonstrate a truly fully-digital implementation for the amplitude modulation (AM) path that meets the strict far-out spectral mask limits without requiring an external SAW filter. The all-digital AM path complements the previously reported all-digital phase-modulation (PM) path in a GSM transmitter [1, 2]. The small-signal digital power amplifier (DPA), which realizes the digital modulation of the carrier’s envelope in the polar transmitter, incorporates a sigma-delta dithering module to enhance its digital-to-analog conversion resolution well beyond the 1024-level offered by its segmented thermometer transistor array. Sophisticated signal processing and filtering are applied to ensure that the noise is shaped such that it meets the strict requirements of the reception (RX) band. Inevitable impairments in the amplitude modulation circuitry, resulting ... ... middle of paper ... ...igher level of integration compared to previous work [4]. Figure 7 shows the chip micrograph of the SoC implemented in 65nm digital CMOS. The TX area occupies about 0.5mm2. Works Cited [1] R. B. Staszewski et al., “All-digital PLL and GSM/EDGE transmitter in 90nm CMOS,” Proc. of IEEE Solid-State Circuits Conf., pp. 316–317, 600, Feb. 2005. [2] R. B. Staszewski et al., “A 24mm2 Quad-Band Single-Chip GSM Radio with Transmitter Calibration in 90nm Digital CMOS,” Proc. of IEEE Solid-State Circuits Conf., pp. 208–209, 607, Feb. 2008. [3] P Cruise et al., “A Digital-to-RF-Amplitude Converter for GSM/GPRS/EDGE in 90-nm Digital CMOS,” IEEE Radio Frequency Integrated Circuits (RFIC) Symp., pp. 21–24, June. 2005. [4] H. Darabi et al., “A Fully Integrated Quad-Band GPRS/EDGE Radio in 0.13μm CMOS,” Proc. of IEEE Solid-State Circuits Conf., pp. 206–207, 607, Feb. 2008.

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