Studying Technology at the University of Texas

Today, as Integrated Circuit has become core of all electronics products, merely able to design an IC is a not sufficient but main challenges lies in high performance & low power design optimization, Robustness with PVT variation tolerance and yield improvement. I know these mysteries can be only be unraveled by design innovation, developing new ideas & algorithms to increase performance of EDA tools. I believe ICS Research Group @ University of Texas, Austin is an ideal choice which can assist me in evolving my ideas to work on these challenges and overcome them , through a well structured curriculum, excellent research faculty and facilities.

My curiosity towards applied science started growing since my high school. During my engineering studies; I found courses on digital design extremely fascinating; devoted a long time in labs & library halls and this addiction motivated me to take it as my major. Through intensive screening, I bagged the chance for a research internship at STMicroelectronics Inc to complete my bachelor thesis in this domain. Bird’s eye view of FPGA Design, exposure to challenges in SoC Design and direct interaction with the designers, was an added fillip to my growing interest in IC Design as a career. My hard work finally paid off when I was awarded with best thesis award in the department along with a job placement offer from STMicroelectronics. A stronghold in Digital & VLSI Design along with extensive practical exposure internship fetched me jobs offers from various chip design companies like Freescale Semiconductor, Texas Instruments, Cypress Semiconductor and STMicroelectronics. Outside my curriculum, I worked on “Digital Image Processing”, while I assisted Dr. Kulbir Singh, in one of his research projects at Thapar Centre for Industrial Research & Development in my eighth semester of B.Engg.

With thoroughly considering my interest area and offered job profile by various semiconductor companies, I decided to join Freescale Semiconductor Inc as IC Design Engineer in Place & Route domain. Today as a Senior IC R&D Engineer, I am involved in research as well as design activities in complete SoC Physical Design flow from RTL to GDSII like Logic Synthesis, Place &Route and Static Timing Analysis. My area of expertise includes “OCV aware design optimization, Leakage & Dynamic Power Reduction, Design Automation and Robust Clock Tree Design for safety clusters & automotive ICs”. My liaison with the Freescale strengthened the essential foundations laid during my under-graduation. The creative atmosphere at Freescale led me to innovate several novel methodologies and implementations, which I filed for reviews with the Freescale’s Patent Review Committee.