Essay on Review of the ARM Processor

Essay on Review of the ARM Processor

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The ARM1176JZF-S (which I will refer to just as ARM) microprocessor belongs to the ARM11 family and uses ARMv6 32-bit RISC architecture.
The AVR has a 2 stage single level pipeline, which is a simple pre-fetch and execute system. The ARM however has a much more complex pipeline system. It uses a 8-stage dual level pipeline; fetch1, fetch2, decode, register, shift, data1, data2 and write-back. This has many advantages over a basic 2 stage pipeline. Parallelism within an instruction allows continued execution for instructions that use both the memory access pathway and the arithmetic pathway in the event that the data cache misses, this means that the requested data was not in the cache and had to be accessed in the data memory. The pipeline can also take alternate paths for different memory operations. Using a direct mapped 128 entry cache, which stores previous branch instructions, the pipeline can make targeted address, or dynamic branch predictions. This means it fills the pipeline with the expected instructions, which reduces the chance that in the event of a branch the whole pipeline must be refilled. When the dynamic prediction is not available it uses a static branch prediction which always predicts a branch with a negative offset, this is particularly helpful for loops and they generally branch back to the start of the loop. The ARM pipeline can also use branch folding, which completely removes the branch instruction from the pipeline.
Both the AVR and ARM use Harvard base architectures, separating the program memory and instruction memory. However the main difference lies in the instruction set. The AVR uses mostly 16-bit instructions, with some 32-bit instructions. The ARM uses 32-bit instructions with 16-bit THUMB in...


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....com/Images/45058A_About-AVR_090913.pdf
ARM, 2004. ARM117656JZ-s Technical Reference Manual.
Available at: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0333h/index.html
ARM, 2007. ARM1176JZF-S User Guide 3.8. Memory configuration.
Available at: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0362c/Babgabdg.html
AVR, ATmega64 Data Sheet.
Davey, I. & Oliveri, P., 2009. The ARM11 Architecture.
Available at: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0362c/Babgabdg.html
Furber, S., 2000. ARM System on Chip Architecture. 2nd ed. London: Pearson Education Limited.
Lin, C., 2004. Set Associative Cache.
Available at: http://www.cs.umd.edu/class/sum2003/cmsc311/Notes/Memory/set.html
Ryzhyk, L., 2006. The ARM Architecture.
Available at: http://www.cse.unsw.edu.au/~cs9244/06/seminars/08-leonidr.pdf

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