In the digital programmable world, FPGA and ASIC play a vital role for complex designs implementation.
In today’s world most of the applications uses FPGA to process the data in the real time and prototyping. The demand for FPGA is increasing because of its performance and reprogramability. The basic building block of FPGA is Logic Block(Configuration Logic Block or Versatile). Many applications, vendors claims the utilization of FPGA or FPGA density in terms of gate counts.
Generated FPGA usage report says about the utilization of the Logic blocks, IO Cells and other dedicated resources like RAM, DSP core…etc.
The usage report will not differentiate about the design component and internal routing. The routing is independent of your design component. This paper talks about to measure the gate count for your design component.
The utilzatoion of the device depends upon the design complexity density of these devices
FPGA architecture and power consumption.
Field-programmable gate arrays (FPGAs) are programmable logic devices that can be configured by the end-user to implement virtually any digital circuit. This is made possible because of the programmable nature of their logic and routing resources. In this paper we intend to discuss about the architecture of the FPGA which has helped in achieving this programmability. The programmable logic and routing interconnect of FPGAs makes them flexible and general purpose but at the same time it makes them larger, slower and more Power consuming than standard cell ASICs. Hence power consumption, its causes and few techniques to minimize the power consumptions are also discussed.
An FPGA comprises of an array of programmable logic...
... middle of paper ...
...ate oxide leakage, and junction leakage and this is seen to be increasing as the transistor size is scaled down (technology scaling). Since FPGAs contain a huge number of transistors, as required to provide programmability, static power consumption is amplified in FPGAs versus in other technologies.
POWER CALCULATION FOR GIVEN DESIGN GOES HERE.
Power optimization techniques:
Dynamic power optimization techniques:
Leakage power optimization techniques:
The utillization of CLB counts depends upon the IOs not on the complexity of the combo logic.
We used tools Synplify Pro on devices Smartfusion-2 OS windows 7.6.1
Y = A AND B AND C AND D.
Y1 = A AND B AND C AND D AND E
Temp = A AND B AND C AND D.
Y2 = Rising_edge(clock) temp;
Y3 = a’b’ + ab + b’c’ +cd’+ cb
Y4 = a’b’ + ab + b’c’ +cd’+ eb
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