# Tutorial On Timing Logic

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EE287- Tutorial on Timing logic • How to time logic? • Underlying equations • Methods used • Why these are used? • Assumptions made • Worked example consisting of at least 3 gates • Pictures, tables and graphs if required. 1. CLOCK: Being students of Electrical Engineering, clock plays a vital role in our digital world. By mentioning clock, I mean “digital clock signal” (clk). It is basically a voltage signal which is similar to a square wave that consists of two voltage levels: High (varies with circuit necessaries) and Low (0). It is represented as follows: Many electronic circuits don’t find the requirement of the clock. Such circuits just calculate the Tp (Propagation Delay) to occur at the final stage output. Whereas, we deal with numerous complex circuits that will malfunction in absence of proper clock timing. Over here, the clock with a constant frequency is used. Clock performs the function of allowing or hindering a process and thereby provide appropriate timing to circuits. They’re used in intricate circuits so as to synchronize different parts in a system. It also takes care of delays associated with the systems. So in simple words, clock functions like the blood that donates signals that makes the inside parts of the chip to work properly. Multiple clocks are also possible. 2. TIMING ANALYSIS: As we all know that data flows in and out of the chip. During this data flow, there’s a necessity to meet some constant i.e. Speed. The timing analysis is way to verify the system timing. It consists of two categories: Dynamic and Static. Characteristics Dynamic Static Based on Simulations Equations/ Formulae Level of Accuracy Very High Low Runtime Extremely Slow Very Fast Applicable Particular parts inside the chip W... ... middle of paper ... ...hed in the earlier register that is supposed to be captures at the current register. Positive skew: It means that clock and data both flows in same direction. Setup time is improved during positive skew but also causes hold violation. Here, the capture clock arrives later to the launch clock. Negative skew: This is just vice-versa of positive skew wherein clock and data both flow in opposite direction. Obviously, it improves hold time but violates setup timing. Here, the capture clock edge comes pretty early than the launch clock. i. Clock Jitter: As we’ve said that, there is difference in arrival of clock at different registers. One of the reasons behind this flaw is aging of oscillators or irregularity in Phase lock loops. Jitter is technically defined as cycle to cycle fluctuations in the given time period. Here the required clock signal is not achieved.