Power Optimisation

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Many different approaches are used to reduce power consumption at the circuit level design. Some of the main techniques are Transistor Sizing, Voltage Scaling, Voltage Islands, Multiple Threshold Voltages and Power Gating. There is a negative effect with each power optimisation technique used at the expense of performance or area. Rabaey (1996) states that Transistor Sizing (TS) technique is used to adjust the size of each transistor (smallest element in the digital system) or gate (group of transistors) for minimum power at the expense of the performance of the gate. Rabaey also states that transistor size is changed only if its place is not critical and it will not affect the whole circuit performance. Another Technique proposed by Pillai, Shin, & Arbor (2001) for power optimisation is Real-time Dynamic Voltage Scaling (RT-DVS) which it is dedicated for embedded computing systems. RT-DVS technique is exploiting the hardware characteristics of processors to reduce energy dissipation by lowering the supply voltage and operating frequency. Pillai, Shin, & Arbor also show that this RT-DVS algorithm closely approach the theoretical lower bound on energy consumption, and can easily reduce energy consumption 20% to 40% in an embedded real-time system. On the other hand the later will be affected by lowering speed of the overall system when using voltage scaling technique (Tawfik & Kursun 2009). Another technique called Voltage Island comes to solve the problem of the RT-DVS technique which different blocks can be run at different voltages for saving power in a non-critical island/block (Puri et al. 2005). Puri et al. also show that Voltage Island may require the use of level-shifters (to change the voltage supply level) when two block...

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