Low-Voltage Current-Mode Realization of Digital Logic Gates using CMOS
In this paper a new technique is introduced for implementing the basic logic function by using analog current-mode techniques. By expanding the logic function in power series expression, and using adder and sub-tractor realization of the basic logic function is simplified. To illustrate the proposed technique, a CMOS circuit for simultaneous realization of the logic function NOT, AND, OR, NAND and XOR is considered. PSPICE simulation results, obtained with ±2V supply, are included.
Key Word: Current Mirror; CMOS analog multiplier; Current mode; Translinear principle; Digital logic circuits;
INTRODUCTION
The current-mode implementation of logic gates is a very important for current mode analog signal processing system. Mixed analog/digital electronic circuits are becoming increasingly important. Digital electronic circuits are mostly designed in CMOS technology. To be able to integrate the digital and analog parts on to one chip, high performance analog CMOS circuits are required (Ismail and Fiez, 1994) and a large number of mixed analog/digital VLSI integrated circuits realized in state-of-the-art digital CMOS technologies are now available (Laker and Sansen, 1994).
In fact the emergence of ICs incorporating mixed analog and digital functions on a single chip has led to an advanced level of analog design (Toumazou et al., 1990). Of particular interest here is the current-mode approach for designing analog ICs. It is well known that current-mode analog signal processing offers some important speed advantages over the traditional voltage-mode signal processing (Allen, 1990). At present current-mode implementations are available for a wide range of analog elect...
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Reliability is one of the most important factors in circuit design. For modern CMOS technology, the circuit reliability is influenced by the shrinking of technology, the reduced supply voltage, higher frequency, and higher circuit density. These factors affects the circuit's probability of soft errors (also called single event upset). In addition, the process variation introduced in the fabrication process is also a big challenge for circuit designers because it makes the same circuit show different characteristics. Moreover, to reduce power consumption of the circuit, the method of reducing supply voltage to near threshold region is used, which is anticipated to have more effects on the reliability of the circuit. So the relationship between single event effect and process variation under near-threshold supply voltage should be analyzed and discussed.
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This proposed multiplier uses a reduction format with predetermined stage heights for having quick results and further minimum power delay product (PDP).When the Simulation results were performed using HSPICE at 0.18µm CMOS technology, the 8x8 multiplier shows optimal speed performance against basic Dadda Tree multiplier and Wallace Tree Multiplier implemented with and without 4-2 Compressors with minimal transistor count and PDP. This proposed reduction format can also be applied to higher order NxN multipliers for high speed
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Electronics can be divided into two branches: analogue and digital. Analogue electrics has developed through the ages of valves in the early 1900s, through transistors to integrated circuits in the 1960s. Analogue electronics deal with the processing of continuously varying signals. In analogue electronics, the amplitude of electrical signal, at any time is proportional to the magnitude of the information being processed. Digital signal consist of a pattern of pulses, usually of the same amplitude. Digital circuits make use of distinct voltage levels, a high level and a low level, to convey information and to control functions within the
Before the multiplexing operation is performed the incoming bit streams are temporally offset from one another by delay for four channels i.e. 25ps, 30ps, 35ps, 40ps. 4*1 multiplexer is used in this paper. And it assembles the higher bit stream from the baseband signal. It also reduces crosstalk.
There is more than one reversible function associated with each irreversible function depending on the number of constant inputs and garbage outputs used and don't care assignments. The circuits that result from synthesizing these embedded reversible functions are different in terms of the number of gates and the number of qubits and hence have different implementation costs. Consequently, the process of embedding an irreversible function into a reversible function is of significant importance and has remained an open problem while being studied in many articles [45,
In 1998 Fuzzy control of head-light intensity of automobiles: design approach was proposed to control the intensity of the head light .Fuzzy logic is a form of many-valued logic in which the truth values of variables may be any real number between 0 and 1.But the drawback was it could only be used in controllers and would never be successfully used in expert systems[1].
Instead of Carry Look ahead adder other multipliers can be used and the work can be extended by using this multiplier in the alu, accumulator unit design and compare the result with the existing design.