Engineering Plan

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Engineering Plan We plan to implement the basic multi-cycle processor design as shown in the textbook, as well as pipelining and “jump and link”. The toughest part of this design will be the datapath control, for which we will be using a FSM. The ALU will implement add, sub, and, or, sll, and slt functions – though a separate block is typically used for shift operations, we felt that putting sll and srl in the ALU would simplify our design. All other basic functions (lw, sw, lui, beq, bne, j) will be implemented as show in the textbook. The processor will have two main stages: load instructions into memory and execute instructions. Special instruction codes will be defined as “stall” and “stop execution” to work in conjunction with the FSM. The global reset will set all memory and registers to 0, and put the FSM in “load instructions mode”. We would like to use one memory module to store both instructions and data (with instructions starting at 0 and going up, and memory starting at the highest address and going down), however this design would present some addressing headaches so we will most likely use separate memory modules for instructions and data. The main part of the pipelining implementation will be the hazard detection unit. We plan to have this work independent of the datapath control FSM as so to simplify FSM design. The hazard detection unit will control muxes to drive register forwarding and will issue stall instructions directly to the instruction register when needed. “Jump and link” will make use of a specially designated register (most likely one of the upper registers, since those aren’t used in the provided test function). Muxes will be used to feed the PC+4 into the regfile and the regfile output into the PC register. The datapath control FSM will control these muxes.
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