Design of a New Full Adder for Fast Arithmetic Operation Processing

1317 Words6 Pages
Addition operation is the most important function of digital system. Adder is only not used for the arithmetic operation but also necessary to all modern computers. Adders occupies critical path in key areas of microprocessor, fast adders are prime requirement for the design of fast processing system. Many fast adders are available but the design of high speed with low power and less area adders are still challenging. In modern computers, multiple ALU’S with wide adders and multiple execution core units on the same chip creates thermal hotspots and large temperature gradients. This affects the circuit and increasing the cooling cost of the system. Adders should have highest performance with least amount of power dissipation and small layout area to minimize the delay.
Historically, VLSI designs have used speed as the performance metric. Portable system as well as fast growth of the power in IC’s, power dissipation becomes main design of the objectives equal to the high performance of the system. For VLSI designs main goal is to designing the power efficient digital system. Generally Ripple Carry Adders are used for all types of adders because of its compact design but it is the slowest adder.
CMOS is the most common digital circuit design style/technique for designing any digital circuit but it is dissipates most of the power during transistor activity. In this brief, an innovative technique is present to implement high speed low area adders in GDI technique shown in [3]. We proposed a power efficient full adder based on the gate diffusion input circuit design. Using this GDI design style, power dissipation in new full adder also it reduces area and propagation delay.
The rest of this brief is organized as follows: a...

... middle of paper ...

...ation,” IEEE Press Series on Microelectronic Systems.
E. Shannon and W. Weaver, The Mathematical Theory of Information. Urbana-Champaign: University of Illinois Press, 1969.
J. P. Uyemura, Circuit Design for CMOS VLSI. Norwell, MA: Kluwer Academic, 1992, pp. 88–129.
M.Morris Mano “Digital Logic and Computer Design”, Pearson Education Publication, Indian reprint 2005.
Alireza Saberkari Shahriar Baradaran Shokouhi, ―A Novel Cmos 1-Bit Full Adder Cell With The Gdi Technique‖, College of Electrical Engineering, Iran University of Science & Technology, Tehran, Iran.
Issam, S., A. Khater, A. Bellaouar and M. I. Elmasry, 1996, ―Circuit tech-niques for CMOS lowpower high performance multipliers‖, IEEE Journal of Solid-State Circuits, 31, 1535-1546.
Zhuang, N. and H. Wu, 1992, ―A new design of the CMOS full adder‖, IEEE Journal of Solid-State Circuits, 27, 840–844.

More about Design of a New Full Adder for Fast Arithmetic Operation Processing

Open Document