Architectures for Scalable Quantum Computation

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1. Introduction

A classical computer represents an implementation of a (sub-) Turing machine that is limited by the laws of classical physics. As such, certain computational problems are either extremely difficult to solve or are intractable (w.r.t. resources). In order to tackle these problems, a super-Turing computational model has been devised and named as the quantum computer [1]. Quantum computation is based on the laws of quantum mechanics and can outperform classical computation in terms of complexity. The power comes from quantum parallelism that is achieved through quantum superposition [2] and entanglement [3]. Computability is unchanged so intractable problems are still unsolvable, but the exponential increase in speed means that the problems that were previously difficult to solve (such as large integer factorisation) are now computable in polynomial time [4].

Quantum computation is still in its infancy and much effort is spent on the engineering problems such as fault-tolerant quantum error correction codes and scalable quantum bit (aka. qubit) implementations and architectures. Unlike a classical computer where a bit is represented by voltage levels or magnetic fields, qubits are implemented by physical objects such as atoms or superconducting devices. The intrinsic properties (e.g. nuclear spin) of these objects provide the necessary basis for quantum information [5]. However, due to these properties, quantum information is fragile and interacts with its environment, destroying the information in the process – this is known as decoherence [6].

Computation can only be carried out on information in a coherent state, hence, a variety of qubit implementation designs, which maximise coherence and fidelity of data, h...

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...pain, 2005, pp. 305-318.

[15] Darshan D. Thaker, Tzvetan S. Metodi, Andrew W. Cross, Isaac L. Chuang, and Frederic T. Chong, "Quantum Memory Hierarchies: Efficient Designs to Match Available Parallelism in Quantum Computing," in Proceedings of the 33rd annual international symposium on Computer Architecture, 2006, pp. 378-390.

[16] Nemanja Isailovic, Mark Whitney, Yatish Patel, and John Kubiatowicz, "Running a Quantum Circuit at the Speed of Data," in Proceedings of the 35th International Symposium on Computer Architecture, 2008, pp. 177-188.

[17] D. Bacon, "Operator quantum error correcting subsystems for self-correcting quantum memories," Phys. Rev A, vol. 73, no. 1 (012340), 2006.

[18] Dean Copsey et al., "Toward a Scalable, Silicon-Based Quantum Computing Architecture," IEEE Journal of Selected Topics in Quantum Electronics, vol. 9, no. 6, pp. 1552-1569, 2003.

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