Standard Cell Characterization

1303 Words3 Pages

Introduction: - In the present scenario, it is very hard to design a circuit using full custom methodology because of the increase in the complexity due to decrease in the feature size. So, most of companies are following the semi-custom approach to reduce the cost & time to market which are the most important parameters for any successful products. To follow the approach of semi-custom, designer need a characterized library of standard cells e.g. logic gates, data buses, sequential building blocks like F/F's etc. That's why, many companies & fabrication plants provide std. cell library with the data sheets containing information about timing, area & power parameters. Overview: - In this report, I will discuss the requirement of std. cells & basic flow for their characterization. The topics of discussion are given below: Basics • Reasons for Characterization • Characterization Flow • Characterization Parameters • Models • Measurement & Verification • Library Formats • Summary • Sources Basics: - The use of the standard cells can be summarized as given below:  Logic units of similar geometry (same height)  Implement basic logic (NAND, NOR, INV, FF, LATCH, complex gates)  Usually come in libraries for a specific technology From the above points, we can conclude that std. cells provide repeatability during layout design which decreases the complexity & make layout formation easy. Also, std. cells are technology dependent so just by selecting library of one technology; we can build any design depending on available cells as shown below. Reasons for Characterization: - The reasons for the characterization are given below: -  Extraction of functionality is complicated  Functional/Delay simulation takes way too long  Power extraction for a whole chip takes too long  Automatic detection of timing constraints (e.g. Setup time) is difficult. Solution: To solve this problem, a simple model for delay, function, constraints and power on cell/gate level is used which provides different characteristics of the cell & thus called cell characterization. Characterization Flow: - The characterization flow for std. cell is a major issue. Many aspects of the characterization demand special attention. The major steps are given below: -  Net list Extraction: In this, the layout for the cell to be characterized is made using any good layout editor for a specific technology & then verified for the technology rules violations & interconnections. After verifying the design, the parasitic extraction is done in which resistance; capacitance & other physical parasitic are being extracted from the design.

Open Document