Performance Evaluation of Discrete Wavelet Transform Architecture

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Discrete wavelet transform has an inherent time-scale locality characteristics which provided an efficient tool for various fields like signal compression, signal analysis, etc. This led to the development of various architectures that implements DWT. The original pixels are highly correlated, thus applying the compression algorithms directly does not provide an efficient compression ratio. Hence, DWT is applied which is a powerful tool to de correlate the image pixels. The 2-D wavelet filters which are separable functions, is implemented first by row-DWT and then column DWT which produces four sub band namely LL, LH, HL and HH in every decomposition level. Filtering a signal corresponds to the mathematical convolution operation of impulse response of the filter to the input signal and that is mathematically represented as,

Due to the large number of computations and storage required in the conventional DWT method, a new approach had been developed, known as “lifting scheme”. It is a new method of constructing wavelet basis, which was introduced by Swelden (1996). The lifting based forward DWT as shown in Fig.3 involves three basic steps as follows:

In this proposed method shown in Fig.7, image pixels are taken in a block manner instead of singe row. First the row processor computes 1D DWT output. Then the result is produced in the vertical manner. The vertical 1D DWT outputs are now ready for the column wise filtering operation; it leads to generate 2D DWT output. From the column processor output components LL, LH, HL and HH, the detailed component LL is useful for the compressed image retrieval. This block row processor takes block of rows which improves the speed of operation as compared with the previously proposed para...

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... and it occupies lesser area compared to both lifting and convolution architectures.

8. CONCLUSION

In this paper, we presented a comparative study of 2D DWT architectures, lifting based implemented using parallel filter and block row processor, fast convolution using booth-Wallace multiplier and distributed arithmetic structure with memory based was made. The effects of area, power, delay I/O pins were analyzed from the synthesis results using Xilinx Spartan 2E family XCs2S50E device. The efficient architecture depends on the low power, area, I/O pins and faster operation. We found that the Distributed Arithmetic based architecture removes the multiplier which in turn provides minimized area, I/O pins and delay for the image size 512 x 512 operated at 20 MHz

Works Cited

Discrete Wavelet Transform (DWT), Lifting, Systolic VLSI, 2-D DWT, Distributed arithmetic.

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