Fpga Essay

NAME: - Parag Rao COURSE: -EE295

TOPIC: - 5 page report SJSUID: -008932014

LOW POWER FPGA

Power consumption is an important issue in modern FPGA’s. Greater performance and complexity has led to higher power dissipation per chip, while the use of deep sub-micron processes has resulted in higher static power in the forms of sub-threshold leakage and gate leakage. Heating solutions for devices with high power dissipation is expensive. If FPGA’s are to be used in portable devices, power consumption needs to be reduced. -powered applications, high power consumption may prohibit the use of FPGA altogether. Consequently, solutions for reducing FPGA power are needed. In this work, I propose a programmable dual-VDD architecture in which the supply voltage of the logic blocks and routing blocks are programmed to reduce power consumption by assigning low-VDD to non-critical paths in the design, while assigning high-VDD to the timing critical paths in the design to meet timing constraints. Evaluation of the effectiveness of different VDD assignment algorithms and architectural implementations show that reducing the supply voltage selectively to the non-critical paths provides significant power savings with minimal impact on performance

Background: - Most of the previous works on power modelling, estimation and reduction in FPGA have focused primarily on dynamic power. In [5], the dynamic power of a Xilinx XC4003A FPGA was analyzed by taking measurements of test designs. [10] analyzes dynamic power consumption in Virtex-II FPGA family. [8, 6] evaluate different FPGA architectures for power efficiency. [11] presents a rout ability-driven bottom-up clustering technique for area and power reduction in clustered FPGAs. Leakage in FPGAs has ca...

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...ifficult. Consequently, if logic blocks are statically determined to be operating at low or high VDD, the placement and routing algorithms need to be modified accordingly as in [11]. However, static assignment of VDD to the blocks may prevent the ability to reduce power consumption or to meet timing constraints for some designs. In contrast, the use of VDD-programmability for each block helps to tune the number of high and low VDD blocks as desired by the application. In this approach, the challenge is in determining the VDD assignments to each block. The need for level converters wherever an low-VDD logic block drives an high-VDD block and the associated delay and energy overheads are an important consideration when performing these VDD assignments. Furthermore, positioning of the level converters influences the ability to assign lower VDD’s to the routing blocks.