Energy-Exposed Instruction Set Architectures
1 Introduction
Power consumption is emerging as a key factor limiting
computational performance in both mobile and tethered
systems. Although there has been significant progress
in low-power circuit design and low-power CAD and some
work in low-power microarchitectures, there has been little
work to date at the level of instruction set architecture
(ISA) design for low power computing.
Modern ISAs such as RISC or VLIW are based on
extensive research into the effects of instruction set design
on performance, and provide a purely performanceoriented
hardware-software interface. These instruction
sets avoid features that would impede a high-performance
implementation. They also avoid providing alternate ways
to perform the same task unless it will increase performance
significantly. Implementations of these ISAs perform
many energy-consuming microarchitectural operations
during execution of each user level instruction and
these dominate total power dissipation. For example, when
executing an integer add instruction on a simple RISC processor
only 1/50th of the total energy consumption is due
to the adder circuitry itself. The rest is dissipated by cache
tag and data accesses, TLBs, register files, pipeline registers,
and pipeline control logic. Modern machine pipelines
have been refined to the point where most of the additional
microarchitecturalwork is performed in a pipelined or parallel
manner that does not affect the throughput or uservisible
latency of a “simple” add instruction. Because their
performance effects can be hidden, there is no incentive
to expose these constituent micro-operations in a purely
performance-oriented hardware-software interface—their
energy consumption is hidden from software.
This short paper reports on ongoing work in the
SCALE (Software-Controlled Architectures for Low-
Energy) project at MIT, where we are developing new
energy-exposed hardware-software interfaces that give
software fine-grain control over energy consumption. The
key idea is to reward compile-time analysis with run-time
energy savings. Our designs provide software with alternative
methods of executing an operation, possibly with the
same performance, but where greater compile-time knowledge
can be used to deactivate unnecessary portions of the
machine microarchitecture.
We are initially focusing on integer applications with
complex control flow as we believe this type of code will
become the energy bottleneck in future embedded systems.
Other highly regular and/or parallel computations
can be readily mapped to energy-efficient computing structures
such as vector/SIMD units [1], reconfigurable units
[5], or application-specific coprocessors [3]. The following
section gives examples of the techniques we are currently
exploring. All simulation numbers we report are
for a MIPS R3000-like processor running gcc-compiled
SPECint95 binaries. Section 3 discusses the technology
we are developing for more sophisticated processor energy
accounting, and Section 4 concludes.
2 Example Energy-Exposed ISA Techniques
Tag-Unchecked Loads and Stores: In some cases,
static analysis can determine that a memory access will always
hit in the cache. For these cases, we provide versions
of load and store instructions that do not check cache tags.
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