Auto-Calibrated Low-Power/High-Speed SRAM Based on a Hybrid Sense Amplifier

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Abstract- In this paper a dual-mode Power/ Performance optimized mode is presented. This dual-operating mode SRAM compensates the delay in Speed-Optimized mode by powering down the pre-charge voltage in the cases the sense amplifiers are slower than designed and a same approach for Power-Optimized mode is applied in which the access time is increased in each iteration. The proposed scheme with a macro cell representing a column with 512 cells is implemented in 0.18um CMOS technology. 45% improvement in read frequency is confirmed in power optimized mode and also a 2× improvement in the failure rate is achieved in comparison to the conventional schemes using the simulation and measurement results.

I. INTRODUCTION

Embedded SRAMs are hugely important components of modern chips. They are used in caches, register files, FIFOs, etc. The growing speed of CPU and DSP reinforces the need to design a more high performance SRAM. On the other hand handheld products such as PDA and cellular phones must very aggressively conserve power. Balancing the tradeoffs between small area, low power and fast reads/writes is an essential part of any SRAM design optimization.

Lower Power Consumption is achieved through performance degradation and higher performance is associated with high power consumption. However in this paper depending on CPU work load and the power source, whether plugged in or battery connected, power or performance is optimized independently.

The read access time is strongly related to the Sense Amplifier, one of the most critical circuits in the periphery of a memory. The use of voltage-mode sense amplifiers causes a speed limitation due to high bit-lines capacitance. Current mode sense amplifiers, on the other hand can great...

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